1. Field of the Invention
This invention relates to tools for designing digital circuits and analyzing digital circuit designs, and particularly to reducing transistor channel length in digital circuit designs.
2. Description of the Related Art
One of the goals in designing synchronous integrated circuits, and particularly very large scale integrated (VLSI) circuits, including application specific integrated circuits (ASICs), general purpose processors, embedded processors, and digital signal processors (DSPs), is high speed operation. To that end, a variety of computer aided design (CAD) tools are used to design, analyze, and simulate integrated circuits. In the process of designing integrated circuits, often referred to as electronic design automation (EDA), a particular integrated circuit (or section thereof) is typically described by a netlist. The netlist is a list of circuit components or cells and interconnections between the circuit components. The various cell input terminals and output terminals through which cells are connected to each other are often referred to as pins or nodes. Determining how fast a given circuit can operate depends in large part on the timing of signals arriving at, and being transmitted from various cells in the circuit. At least two main approaches are used in EDA for timing verification and analysis during the circuit design process, dynamic timing and static timing.
Traditionally, dynamic timing analysis has been used to verify the functionality and timing of an entire design or blocks within a design. Dynamic timing analysis uses vectors provided by the designer and performs logic simulation with timing values to verify the timing behavior of the circuit. Dynamic timing analysis is difficult to use because the designer must provide the input signal patterns and analyze the output wave forms to verify that the circuit functions correctly at the intended speed. Dynamic verification has the advantage that the timing behavior of any design can be analyzed and dynamic verification offers a high degree of accuracy by correctly modeling the Boolean interaction between signals.
However, designers have to create separate timing and functional vectors for dynamic timing analysis, and thus the quality of the dynamic timing analysis is limited by the input stimuli provided by the designer. Additionally, it can be difficult to create timing vectors that will exercise each path in the design exhaustively. For example, if the designer does not correctly specify the input condition that triggers the worst-case delay path in the circuit, the dynamic timing analysis may result in an optimistic value for the circuit speed. Finally, dynamic timing analysis requires extensive computer resources because a large number of input signal patterns must be simulated to offer a high degree of confidence in the results. The vector generation problem is magnified as the size and complexity of designs increase. The advent of larger designs and enormous vector sets make dynamic simulation a serious bottleneck in design flows.
To combat many of these problems, static timing verification is increasingly being used. Static timing analysis is an exhaustive method of analyzing, debugging and validating the timing performance of a design. This is achieved by breaking down the design into sets of paths. A static timing analyzer assesses circuit timing performance by relying upon timing attributes, as specified in a library of timing models, for individual circuit components in the netlist. The library of timing models includes timing information for each circuit component in the netlist. The timing information includes such information as the input pin capacitance, input-to-output delay, and output drive strengths. Combining this library along with a design netlist, a static timing analyzer generates critical path timing information statically without knowledge of the design""s logical functionality. The delay of each path in the design is calculated and checked against timing assertions for any possible violation that would effect performance or limit operating frequency. Different types of checks that can be performed by a static-timing analysis tool include setup time (the length of time that a data input pin must be stable before an active clock transition), hold time (the length of time that a data input pin must be stable after an active clock transition), recovery (the length of time that an asynchronous control input pin must be stable before a clock active-edge transition), removal (the length of time that an asynchronous control input pin must be stable after a clock-active edge transition) and clock pulse width. Static timing analysis is exhaustive in that every path in the design is checked for timing violations. This is a benefit over dynamic simulators, which would require a large number of vectors in order to provide the same level of timing coverage. Since static timing analysis is not based on functional vectors, it is typically fast and can accommodate large designs. Static timing analysis does suffer from at least one drawback, false paths. Because the analysis typically considers all possible paths, some paths which will logically never be used can be included in the analysis unnecessarily.
Static timing verification can identify those cells and paths that are critical to the operation, but that is only part of the process. Design changes must be made to reduce or eliminate timing violations. One solution to improve timing along a critical path is to replace one or more of the field effect transistors (FETs) along the path (e.g., transistors in a cell along the path) with a similar transistor having a shorter channel length between the source and drain regions, thereby reducing the channel transit time (i.e., the average time required for an electron to traverse a FETs channel from source to drain), as is well know by those having ordinary skill in the art of circuit design. Because the transit time is reduced, propagation times associated with the transistor are improved, and paths that previously had timing violations can be brought within timing requirements.
Unfortunately, replacing a given transistor with a similar transistor having a shorter channel length does have at least one drawback. Leakage currents associated with a transistor tend to increase with decreasing channel length. For example, one common component to transistor leakage currents, a subthreshold channel current, is known to be inversely proportional to channel length. Increased leakage currents are a concern of integrated circuit designers because the integrated circuit usually has a defined power budget, e.g., approximately 8 W for a processor designed for portable computers, and any increase power drain associated with leakage currents must fall within the power budget.
Accordingly, it is desirable to have integrated circuit design tools and techniques for selective sizing down the channel lengths of transistors in timing critical paths in the integrated circuit, while staying within a power budget.
It has been discovered that tools and techniques used in conjunction with integrated circuit path timing information can selectively reduce the channel length of transistors in cells associated with the most critical paths in an integrated circuit, while keeping the overall integrated circuit design within a specified power budget. Moreover, by targeting pins of cells (and thus their associated transistors) that are used by multiple paths, and/or that offer the greatest potential speed improvement, timing violations along critical paths can be reduced or eliminated with a relatively few number of replacements. Paths within a certain timing violation range are selected for analysis. The pins within those paths are ranked by pin criticality, which can depend on, for example, the number of times a particular pin occurs in any path, the timing enhancement associated with replacing a cell having that pin, and the impact of replacing a cell having that pin would have on the power budget. Transistors within cells (or entire cells) associated with pins are replaced based on the pin criticality until timing improvements are sufficient to remove a path from the range of paths being examined. Successive paths, and ranges of paths are analyzed until the power budget is exceeded, or no more improvements can be made.
Accordingly, one aspect of the present invention provides a method for selectively decreasing a channel length of a transistor to be used in a semiconductor device. A timing database is provided. The timing database includes a plurality of circuit paths, at least two circuit paths each representing a path through a plurality of pins in a circuit design. Each of at least two of the plurality pins in each of the at least two circuit paths is associated with one of an input and an output of a respective cell in the circuit design. Each respective cell has at least one transistor, and each of the at least two circuit paths has an associated timing violation providing information about violation of at least one timing assertion. A subset of circuit paths is selected from the timing database. The subset includes at least one of the at least two circuit paths. The timing violation of each circuit path in the subset is within a range of timing violations. A pin criticality for each pin in each path within the subset is determined. At least one cell associated with a pin in the subset of circuit paths is replaced with a cell having a transistor with a reduced channel length. Replacement depends on the pin criticality of the pin associated with the at least one cell.
In another aspect of the invention, an apparatus includes a processor, a memory coupled to the processor, and a circuit design program at least partially storable in the memory and executable on the processor. The program includes a path selection routine for selecting a plurality of paths in a circuit design, at least one path including a plurality of pins, and having an associated timing violation providing information about violation of at least one timing assertion. The program also includes a pin criticality routine for determining a pin criticality for at least one pin in the at least one path, and a cell replacement routine for selectively replacing at least one cell associated with the at least one pin in the at least one path with a cell having a reduced channel length transistor. Replacement depends on the pin criticality of the at least one pin in the at least one path.